From 81e25ee5c333d0b419515eb5ae88b01ba2cdca3a Mon Sep 17 00:00:00 2001 From: Alois Wohlschlager Date: Sun, 16 Apr 2023 16:16:46 +0200 Subject: [PATCH] stub: clarify instruction cache coherence --- rust/stub/src/pe_loader.rs | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/rust/stub/src/pe_loader.rs b/rust/stub/src/pe_loader.rs index b60faaa..ccb869a 100644 --- a/rust/stub/src/pe_loader.rs +++ b/rust/stub/src/pe_loader.rs @@ -17,7 +17,7 @@ const UEFI_PAGE_BITS: usize = 12; const UEFI_PAGE_MASK: usize = (1 << UEFI_PAGE_BITS) - 1; #[cfg(target_arch = "x86_64")] -fn flush_instruction_cache(_start: *const u8, _length: usize) { +fn make_instruction_cache_coherent(_start: *const u8, _length: usize) { // x86_64 mandates coherent instruction cache } @@ -98,7 +98,10 @@ impl Image { return Err(Status::INCOMPATIBLE_VERSION.into()); } - flush_instruction_cache(image.as_ptr(), image.len()); + // On some platforms, the instruction cache is not coherent with the data cache. + // We don't want to execute stale icache contents instead of the code we just loaded. + // Platform-specific flushes need to be performed to prevent this from happening. + make_instruction_cache_coherent(image.as_ptr(), image.len()); if pe.entry >= image.len() { return Err(Status::LOAD_ERROR.into());